-- Copyright (C) 1991-2012 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version"

-- DATE "04/15/2013 15:33:13"

-- 
-- Device: Altera EP4CE10E22C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	DDS_V1 IS
    PORT (
	c0 : OUT std_logic;
	inclk0 : IN std_logic;
	areset : IN std_logic;
	c1 : OUT std_logic;
	c2 : OUT std_logic;
	locked : OUT std_logic;
	fsmc_db : INOUT std_logic_vector(15 DOWNTO 0);
	fsmc_wrn : IN std_logic;
	fsmc_rdn : IN std_logic;
	fsmc_resetn : IN std_logic;
	fsmc_csn : IN std_logic;
	fsmc_ab : IN std_logic_vector(2 DOWNTO 0);
	q : OUT std_logic_vector(15 DOWNTO 0);
	CLK : IN std_logic
	);
END DDS_V1;

-- Design Ports Information
-- c0	=>  Location: PIN_43,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- c1	=>  Location: PIN_138,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- c2	=>  Location: PIN_46,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- locked	=>  Location: PIN_39,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[15]	=>  Location: PIN_83,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[14]	=>  Location: PIN_104,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[13]	=>  Location: PIN_100,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[12]	=>  Location: PIN_66,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[11]	=>  Location: PIN_64,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[10]	=>  Location: PIN_135,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[9]	=>  Location: PIN_120,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[8]	=>  Location: PIN_136,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[7]	=>  Location: PIN_98,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[6]	=>  Location: PIN_127,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[5]	=>  Location: PIN_86,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[4]	=>  Location: PIN_32,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[3]	=>  Location: PIN_85,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[2]	=>  Location: PIN_103,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[1]	=>  Location: PIN_99,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q[0]	=>  Location: PIN_84,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[15]	=>  Location: PIN_132,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[14]	=>  Location: PIN_125,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[13]	=>  Location: PIN_128,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[12]	=>  Location: PIN_105,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[11]	=>  Location: PIN_133,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[10]	=>  Location: PIN_121,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[9]	=>  Location: PIN_119,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[8]	=>  Location: PIN_124,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[7]	=>  Location: PIN_114,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[6]	=>  Location: PIN_106,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[5]	=>  Location: PIN_110,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[4]	=>  Location: PIN_115,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[3]	=>  Location: PIN_87,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[2]	=>  Location: PIN_112,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[1]	=>  Location: PIN_113,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_db[0]	=>  Location: PIN_111,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- areset	=>  Location: PIN_88,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- inclk0	=>  Location: PIN_23,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CLK	=>  Location: PIN_24,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_resetn	=>  Location: PIN_89,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_ab[0]	=>  Location: PIN_25,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_rdn	=>  Location: PIN_31,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_csn	=>  Location: PIN_28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_wrn	=>  Location: PIN_30,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_ab[2]	=>  Location: PIN_129,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- fsmc_ab[1]	=>  Location: PIN_126,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF DDS_V1 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_c0 : std_logic;
SIGNAL ww_inclk0 : std_logic;
SIGNAL ww_areset : std_logic;
SIGNAL ww_c1 : std_logic;
SIGNAL ww_c2 : std_logic;
SIGNAL ww_locked : std_logic;
SIGNAL ww_fsmc_wrn : std_logic;
SIGNAL ww_fsmc_rdn : std_logic;
SIGNAL ww_fsmc_resetn : std_logic;
SIGNAL ww_fsmc_csn : std_logic;
SIGNAL ww_fsmc_ab : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_q : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_CLK : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst2|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0);
SIGNAL \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(17 DOWNTO 0);
SIGNAL \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\ : std_logic_vector(17 DOWNTO 0);
SIGNAL \inst3|wr~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|wr~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \fsmc_resetn~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|RAM_CLK~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \areset~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst|Add1~0_combout\ : std_logic;
SIGNAL \inst|Add1~2_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[6]~19_combout\ : std_logic;
SIGNAL \inst|Equal4~0_combout\ : std_logic;
SIGNAL \inst|Selector8~0_combout\ : std_logic;
SIGNAL \inst|Selector8~1_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[0]~24_combout\ : std_logic;
SIGNAL \inst|wr~combout\ : std_logic;
SIGNAL \inst|clk_para[7]~2_combout\ : std_logic;
SIGNAL \inst|clk_para[4]~5_combout\ : std_logic;
SIGNAL \inst|clk_para[1]~8_combout\ : std_logic;
SIGNAL \inst3|wr~combout\ : std_logic;
SIGNAL \fsmc_db[15]~input_o\ : std_logic;
SIGNAL \fsmc_db[10]~input_o\ : std_logic;
SIGNAL \CLK~input_o\ : std_logic;
SIGNAL \fsmc_wrn~input_o\ : std_logic;
SIGNAL \inst3|wr~clkctrl_outclk\ : std_logic;
SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
SIGNAL \inst|wr~clkctrl_outclk\ : std_logic;
SIGNAL \inst|ram_clk_limit[7]~feeder_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[4]~feeder_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[1]~feeder_combout\ : std_logic;
SIGNAL \inst|addr_set[7]~feeder_combout\ : std_logic;
SIGNAL \inst|addr_set[6]~feeder_combout\ : std_logic;
SIGNAL \inst|addr_set[5]~feeder_combout\ : std_logic;
SIGNAL \inst|addr_set[4]~feeder_combout\ : std_logic;
SIGNAL \inst|addr_set[3]~feeder_combout\ : std_logic;
SIGNAL \inst3|outb[11]~feeder_combout\ : std_logic;
SIGNAL \inst3|outa[10]~feeder_combout\ : std_logic;
SIGNAL \inst3|outb[10]~feeder_combout\ : std_logic;
SIGNAL \inst3|outa[7]~feeder_combout\ : std_logic;
SIGNAL \fsmc_csn~input_o\ : std_logic;
SIGNAL \fsmc_rdn~input_o\ : std_logic;
SIGNAL \inst3|rd~combout\ : std_logic;
SIGNAL \inclk0~input_o\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_outclk\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_locked\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|pll_lock_sync~feeder_combout\ : std_logic;
SIGNAL \areset~input_o\ : std_logic;
SIGNAL \areset~inputclkctrl_outclk\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|pll_lock_sync~q\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|locked~combout\ : std_logic;
SIGNAL \fsmc_ab[0]~input_o\ : std_logic;
SIGNAL \inst|ram_wr_flag~0_combout\ : std_logic;
SIGNAL \fsmc_resetn~input_o\ : std_logic;
SIGNAL \fsmc_resetn~inputclkctrl_outclk\ : std_logic;
SIGNAL \inst|ram_wr_flag~q\ : std_logic;
SIGNAL \inst|RAM_WEN~0_combout\ : std_logic;
SIGNAL \inst|RAM_WEN~q\ : std_logic;
SIGNAL \inst|ram_clk_div~0_combout\ : std_logic;
SIGNAL \inst|ram_clk_div~q\ : std_logic;
SIGNAL \inst|RAM_CLK~feeder_combout\ : std_logic;
SIGNAL \inst|RAM_CLK~q\ : std_logic;
SIGNAL \inst|RAM_CLK~clkctrl_outclk\ : std_logic;
SIGNAL \fsmc_db[0]~input_o\ : std_logic;
SIGNAL \fsmc_ab[1]~input_o\ : std_logic;
SIGNAL \fsmc_ab[2]~input_o\ : std_logic;
SIGNAL \inst3|Decoder0~1_combout\ : std_logic;
SIGNAL \fsmc_db[13]~input_o\ : std_logic;
SIGNAL \fsmc_db[12]~input_o\ : std_logic;
SIGNAL \fsmc_db[14]~input_o\ : std_logic;
SIGNAL \inst|Equal0~0_combout\ : std_logic;
SIGNAL \fsmc_db[3]~input_o\ : std_logic;
SIGNAL \fsmc_db[6]~input_o\ : std_logic;
SIGNAL \fsmc_db[4]~input_o\ : std_logic;
SIGNAL \fsmc_db[5]~input_o\ : std_logic;
SIGNAL \inst|Equal0~2_combout\ : std_logic;
SIGNAL \inst|Equal0~3_combout\ : std_logic;
SIGNAL \fsmc_db[1]~input_o\ : std_logic;
SIGNAL \fsmc_db[11]~input_o\ : std_logic;
SIGNAL \fsmc_db[8]~input_o\ : std_logic;
SIGNAL \fsmc_db[9]~input_o\ : std_logic;
SIGNAL \inst3|outa[9]~feeder_combout\ : std_logic;
SIGNAL \inst|Equal0~1_combout\ : std_logic;
SIGNAL \inst|Equal4~1_combout\ : std_logic;
SIGNAL \inst|Selector2~5_combout\ : std_logic;
SIGNAL \inst|Selector4~0_combout\ : std_logic;
SIGNAL \inst|ddsSta.WR_ONE_BYTE~q\ : std_logic;
SIGNAL \inst3|Decoder0~0_combout\ : std_logic;
SIGNAL \inst|Selector24~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[0]~feeder_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[15]~0_combout\ : std_logic;
SIGNAL \inst|Selector7~0_combout\ : std_logic;
SIGNAL \inst|ddsSta.SET_ADDR~q\ : std_logic;
SIGNAL \inst|addr_set[0]~0_combout\ : std_logic;
SIGNAL \inst|clk_para[6]~3_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[6]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector5~0_combout\ : std_logic;
SIGNAL \inst|ddsSta.SET_FRE_RANGE~q\ : std_logic;
SIGNAL \fsmc_db[2]~input_o\ : std_logic;
SIGNAL \inst|Equal5~0_combout\ : std_logic;
SIGNAL \inst|always0~0_combout\ : std_logic;
SIGNAL \inst|always0~1_combout\ : std_logic;
SIGNAL \inst|ddsSta~20_combout\ : std_logic;
SIGNAL \inst|ddsSta.SET_FRE_PARA~q\ : std_logic;
SIGNAL \inst3|outb[1]~feeder_combout\ : std_logic;
SIGNAL \inst|clk_range[1]~0_combout\ : std_logic;
SIGNAL \inst|clk_range[0]~1_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[9]~0_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[9]~1_combout\ : std_logic;
SIGNAL \inst|clk_para[3]~6_combout\ : std_logic;
SIGNAL \inst3|outb[5]~feeder_combout\ : std_logic;
SIGNAL \inst|clk_para[5]~4_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[5]~feeder_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~1_combout\ : std_logic;
SIGNAL \inst3|outb[2]~feeder_combout\ : std_logic;
SIGNAL \inst|clk_para[2]~7_combout\ : std_logic;
SIGNAL \inst|clk_para[0]~9_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[0]~feeder_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~2_combout\ : std_logic;
SIGNAL \inst3|outb[8]~feeder_combout\ : std_logic;
SIGNAL \inst|clk_para[8]~1_combout\ : std_logic;
SIGNAL \inst|ram_clk_limit[8]~feeder_combout\ : std_logic;
SIGNAL \inst3|outb[9]~feeder_combout\ : std_logic;
SIGNAL \inst|clk_para[9]~0_combout\ : std_logic;
SIGNAL \inst|Selector8~2_combout\ : std_logic;
SIGNAL \inst|dds_out_en~q\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~0_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~3_combout\ : std_logic;
SIGNAL \inst|addr_set[2]~feeder_combout\ : std_logic;
SIGNAL \inst|Add1~1\ : std_logic;
SIGNAL \inst|Add1~3\ : std_logic;
SIGNAL \inst|Add1~4_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~8_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~5_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR[0]~6_combout\ : std_logic;
SIGNAL \inst|Add1~5\ : std_logic;
SIGNAL \inst|Add1~7\ : std_logic;
SIGNAL \inst|Add1~8_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~10_combout\ : std_logic;
SIGNAL \inst|Add1~9\ : std_logic;
SIGNAL \inst|Add1~11\ : std_logic;
SIGNAL \inst|Add1~13\ : std_logic;
SIGNAL \inst|Add1~14_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~13_combout\ : std_logic;
SIGNAL \fsmc_db[7]~input_o\ : std_logic;
SIGNAL \inst3|outb[7]~feeder_combout\ : std_logic;
SIGNAL \inst3|outb[3]~feeder_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[1]~8_cout\ : std_logic;
SIGNAL \inst|ram_buf_size[1]~10\ : std_logic;
SIGNAL \inst|ram_buf_size[2]~12\ : std_logic;
SIGNAL \inst|ram_buf_size[3]~14\ : std_logic;
SIGNAL \inst|ram_buf_size[4]~16\ : std_logic;
SIGNAL \inst|ram_buf_size[5]~18\ : std_logic;
SIGNAL \inst|ram_buf_size[6]~20\ : std_logic;
SIGNAL \inst|ram_buf_size[7]~21_combout\ : std_logic;
SIGNAL \inst|Equal2~0_combout\ : std_logic;
SIGNAL \inst|Selector2~4_combout\ : std_logic;
SIGNAL \inst|ddsSta.DDS_PAUSE~q\ : std_logic;
SIGNAL \inst|ram_buf_size[7]~23_combout\ : std_logic;
SIGNAL \inst|Add1~12_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~12_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[5]~17_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[4]~15_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[3]~13_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[2]~11_combout\ : std_logic;
SIGNAL \inst|ram_buf_size[1]~9_combout\ : std_logic;
SIGNAL \inst|LessThan1~1_cout\ : std_logic;
SIGNAL \inst|LessThan1~3_cout\ : std_logic;
SIGNAL \inst|LessThan1~5_cout\ : std_logic;
SIGNAL \inst|LessThan1~7_cout\ : std_logic;
SIGNAL \inst|LessThan1~9_cout\ : std_logic;
SIGNAL \inst|LessThan1~11_cout\ : std_logic;
SIGNAL \inst|LessThan1~13_cout\ : std_logic;
SIGNAL \inst|LessThan1~14_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~4_combout\ : std_logic;
SIGNAL \inst|addr_set[1]~feeder_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~7_combout\ : std_logic;
SIGNAL \inst|Add1~6_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~9_combout\ : std_logic;
SIGNAL \inst|Add1~10_combout\ : std_logic;
SIGNAL \inst|RAM_ADDR~11_combout\ : std_logic;
SIGNAL \inst|WideOr11~0_combout\ : std_logic;
SIGNAL \inst|Selector23~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[1]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector22~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[2]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector21~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[3]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector20~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[4]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector19~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[5]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector18~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[6]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector17~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[7]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector16~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[8]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector15~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[9]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector14~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[10]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector13~0_combout\ : std_logic;
SIGNAL \inst3|outb[12]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector12~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[12]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector11~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[13]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector10~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[14]~feeder_combout\ : std_logic;
SIGNAL \inst|Selector9~0_combout\ : std_logic;
SIGNAL \inst|RAM_DAT[15]~feeder_combout\ : std_logic;
SIGNAL \inst2|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0);
SIGNAL \inst3|outb\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst3|outa\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst1|altsyncram_component|auto_generated|q_a\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst|ram_clk_limit\ : std_logic_vector(31 DOWNTO 0);
SIGNAL \inst|ram_buf_size\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst|dds_ram_data\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst|clk_range\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst|clk_para\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \inst|addr_set\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst|RAM_DAT\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst|RAM_ADDR\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_areset~inputclkctrl_outclk\ : std_logic;
SIGNAL \ALT_INV_fsmc_ab[0]~input_o\ : std_logic;

BEGIN

c0 <= ww_c0;
ww_inclk0 <= inclk0;
ww_areset <= areset;
c1 <= ww_c1;
c2 <= ww_c2;
locked <= ww_locked;
ww_fsmc_wrn <= fsmc_wrn;
ww_fsmc_rdn <= fsmc_rdn;
ww_fsmc_resetn <= fsmc_resetn;
ww_fsmc_csn <= fsmc_csn;
ww_fsmc_ab <= fsmc_ab;
q <= ww_q;
ww_CLK <= CLK;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\inst2|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \inclk0~input_o\);

\inst2|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst2|altpll_component|auto_generated|pll1_CLK_bus\(0);
\inst2|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst2|altpll_component|auto_generated|pll1_CLK_bus\(1);
\inst2|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst2|altpll_component|auto_generated|pll1_CLK_bus\(2);
\inst2|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst2|altpll_component|auto_generated|pll1_CLK_bus\(3);
\inst2|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst2|altpll_component|auto_generated|pll1_CLK_bus\(4);

\inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \inst|RAM_DAT\(15) & \inst|RAM_DAT\(14) & \inst|RAM_DAT\(13) & \inst|RAM_DAT\(12) & \inst|RAM_DAT\(11) & \inst|RAM_DAT\(10) & \inst|RAM_DAT\(9) & 
\inst|RAM_DAT\(8) & \inst|RAM_DAT\(7) & \inst|RAM_DAT\(6) & \inst|RAM_DAT\(5) & \inst|RAM_DAT\(4) & \inst|RAM_DAT\(3) & \inst|RAM_DAT\(2) & \inst|RAM_DAT\(1) & \inst|RAM_DAT\(0));

\inst1|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst|RAM_ADDR\(7) & \inst|RAM_ADDR\(6) & \inst|RAM_ADDR\(5) & \inst|RAM_ADDR\(4) & \inst|RAM_ADDR\(3) & \inst|RAM_ADDR\(2) & \inst|RAM_ADDR\(1) & 
\inst|RAM_ADDR\(0));

\inst1|altsyncram_component|auto_generated|q_a\(0) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(0);
\inst1|altsyncram_component|auto_generated|q_a\(1) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(1);
\inst1|altsyncram_component|auto_generated|q_a\(2) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(2);
\inst1|altsyncram_component|auto_generated|q_a\(3) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(3);
\inst1|altsyncram_component|auto_generated|q_a\(4) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(4);
\inst1|altsyncram_component|auto_generated|q_a\(5) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(5);
\inst1|altsyncram_component|auto_generated|q_a\(6) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(6);
\inst1|altsyncram_component|auto_generated|q_a\(7) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(7);
\inst1|altsyncram_component|auto_generated|q_a\(8) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(8);
\inst1|altsyncram_component|auto_generated|q_a\(9) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(9);
\inst1|altsyncram_component|auto_generated|q_a\(10) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(10);
\inst1|altsyncram_component|auto_generated|q_a\(11) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(11);
\inst1|altsyncram_component|auto_generated|q_a\(12) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(12);
\inst1|altsyncram_component|auto_generated|q_a\(13) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(13);
\inst1|altsyncram_component|auto_generated|q_a\(14) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(14);
\inst1|altsyncram_component|auto_generated|q_a\(15) <= \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(15);

\inst3|wr~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst3|wr~combout\);

\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);

\inst|wr~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|wr~combout\);

\inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_INCLK_bus\ <= (vcc & vcc & vcc & \inst2|altpll_component|auto_generated|wire_pll1_clk\(0));

\inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst2|altpll_component|auto_generated|wire_pll1_clk\(1));

\inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst2|altpll_component|auto_generated|wire_pll1_clk\(2));

\fsmc_resetn~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \fsmc_resetn~input_o\);

\inst|RAM_CLK~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|RAM_CLK~q\);

\areset~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \areset~input_o\);
\ALT_INV_areset~inputclkctrl_outclk\ <= NOT \areset~inputclkctrl_outclk\;
\ALT_INV_fsmc_ab[0]~input_o\ <= NOT \fsmc_ab[0]~input_o\;

-- Location: LCCOMB_X28_Y17_N12
\inst|Add1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~0_combout\ = \inst|RAM_ADDR\(0) $ (VCC)
-- \inst|Add1~1\ = CARRY(\inst|RAM_ADDR\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(0),
	datad => VCC,
	combout => \inst|Add1~0_combout\,
	cout => \inst|Add1~1\);

-- Location: FF_X30_Y17_N19
\inst|ram_buf_size[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[6]~19_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(6));

-- Location: LCCOMB_X28_Y17_N14
\inst|Add1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~2_combout\ = (\inst|RAM_ADDR\(1) & (!\inst|Add1~1\)) # (!\inst|RAM_ADDR\(1) & ((\inst|Add1~1\) # (GND)))
-- \inst|Add1~3\ = CARRY((!\inst|Add1~1\) # (!\inst|RAM_ADDR\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(1),
	datad => VCC,
	cin => \inst|Add1~1\,
	combout => \inst|Add1~2_combout\,
	cout => \inst|Add1~3\);

-- Location: LCCOMB_X30_Y17_N18
\inst|ram_buf_size[6]~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[6]~19_combout\ = (\inst3|outb\(6) & ((GND) # (!\inst|ram_buf_size[5]~18\))) # (!\inst3|outb\(6) & (\inst|ram_buf_size[5]~18\ $ (GND)))
-- \inst|ram_buf_size[6]~20\ = CARRY((\inst3|outb\(6)) # (!\inst|ram_buf_size[5]~18\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101010101111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(6),
	datad => VCC,
	cin => \inst|ram_buf_size[5]~18\,
	combout => \inst|ram_buf_size[6]~19_combout\,
	cout => \inst|ram_buf_size[6]~20\);

-- Location: FF_X28_Y19_N27
\inst|ram_clk_limit[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[7]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(7));

-- Location: FF_X28_Y19_N13
\inst|ram_clk_limit[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[4]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(4));

-- Location: FF_X28_Y19_N23
\inst|ram_clk_limit[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[1]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(1));

-- Location: FF_X29_Y17_N11
\inst|ram_buf_size[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[0]~24_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(0));

-- Location: FF_X30_Y19_N19
\inst|addr_set[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[3]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(3));

-- Location: FF_X30_Y19_N5
\inst|addr_set[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[4]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(4));

-- Location: FF_X30_Y19_N15
\inst|addr_set[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[5]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(5));

-- Location: FF_X30_Y19_N25
\inst|addr_set[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[6]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(6));

-- Location: FF_X30_Y19_N27
\inst|addr_set[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[7]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(7));

-- Location: FF_X26_Y19_N1
\inst3|outb[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[15]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(15));

-- Location: FF_X26_Y19_N7
\inst3|outa[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[15]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(15));

-- Location: FF_X25_Y19_N7
\inst3|outa[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outa[10]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(10));

-- Location: FF_X25_Y19_N27
\inst3|outa[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outa[7]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(7));

-- Location: LCCOMB_X25_Y19_N8
\inst|Equal4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal4~0_combout\ = (\inst3|outa\(3) & (!\inst3|outa\(2) & !\inst3|outa\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(3),
	datab => \inst3|outa\(2),
	datad => \inst3|outa\(1),
	combout => \inst|Equal4~0_combout\);

-- Location: LCCOMB_X24_Y19_N26
\inst|Selector8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector8~0_combout\ = (\inst3|outa\(2) & ((\inst3|outa\(1)))) # (!\inst3|outa\(2) & (\inst3|outa\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(0),
	datac => \inst3|outa\(2),
	datad => \inst3|outa\(1),
	combout => \inst|Selector8~0_combout\);

-- Location: LCCOMB_X24_Y19_N12
\inst|Selector8~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector8~1_combout\ = (\inst|Selector8~0_combout\ & (\inst|Equal0~3_combout\ & ((\inst|dds_out_en~q\) # (!\inst3|outa\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(1),
	datab => \inst|dds_out_en~q\,
	datac => \inst|Selector8~0_combout\,
	datad => \inst|Equal0~3_combout\,
	combout => \inst|Selector8~1_combout\);

-- Location: FF_X29_Y19_N21
\inst|clk_para[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[7]~2_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(7));

-- Location: FF_X25_Y17_N23
\inst|clk_para[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[4]~5_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(4));

-- Location: FF_X29_Y19_N3
\inst|clk_para[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[1]~8_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(1));

-- Location: FF_X30_Y17_N27
\inst3|outb[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[4]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(4));

-- Location: LCCOMB_X29_Y17_N10
\inst|ram_buf_size[0]~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[0]~24_combout\ = (\inst|ram_buf_size[7]~23_combout\ & (!\inst3|outb\(0))) # (!\inst|ram_buf_size[7]~23_combout\ & ((\inst|ram_buf_size\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|outb\(0),
	datac => \inst|ram_buf_size\(0),
	datad => \inst|ram_buf_size[7]~23_combout\,
	combout => \inst|ram_buf_size[0]~24_combout\);

-- Location: FF_X26_Y19_N9
\inst3|outb[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[14]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(14));

-- Location: FF_X26_Y19_N3
\inst3|outb[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[13]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(13));

-- Location: FF_X26_Y19_N21
\inst3|outb[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[11]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(11));

-- Location: FF_X26_Y19_N31
\inst3|outb[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[10]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(10));

-- Location: LCCOMB_X1_Y11_N16
\inst|wr\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|wr~combout\ = LCELL((!\fsmc_csn~input_o\) # (!\fsmc_wrn~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \fsmc_wrn~input_o\,
	datad => \fsmc_csn~input_o\,
	combout => \inst|wr~combout\);

-- Location: LCCOMB_X29_Y19_N20
\inst|clk_para[7]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[7]~2_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_para\(7))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_PARA~q\ & (\inst3|outb\(7))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & ((\inst|clk_para\(7))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110001011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(7),
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(7),
	datad => \inst|ddsSta.SET_FRE_PARA~q\,
	combout => \inst|clk_para[7]~2_combout\);

-- Location: LCCOMB_X25_Y17_N22
\inst|clk_para[4]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[4]~5_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & ((\inst|clk_para\(4)))) # (!\fsmc_ab[0]~input_o\ & (\inst3|outb\(4))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(4)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(4),
	datab => \inst|ddsSta.SET_FRE_PARA~q\,
	datac => \inst|clk_para\(4),
	datad => \fsmc_ab[0]~input_o\,
	combout => \inst|clk_para[4]~5_combout\);

-- Location: LCCOMB_X29_Y19_N2
\inst|clk_para[1]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[1]~8_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & (\inst|clk_para\(1))) # (!\fsmc_ab[0]~input_o\ & ((\inst3|outb\(1)))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(1),
	datad => \inst3|outb\(1),
	combout => \inst|clk_para[1]~8_combout\);

-- Location: LCCOMB_X1_Y11_N14
\inst3|wr\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|wr~combout\ = LCELL((!\fsmc_csn~input_o\) # (!\fsmc_wrn~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \fsmc_wrn~input_o\,
	datad => \fsmc_csn~input_o\,
	combout => \inst3|wr~combout\);

-- Location: IOIBUF_X13_Y24_N15
\fsmc_db[15]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(15),
	o => \fsmc_db[15]~input_o\);

-- Location: IOIBUF_X23_Y24_N15
\fsmc_db[10]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(10),
	o => \fsmc_db[10]~input_o\);

-- Location: IOIBUF_X0_Y11_N15
\CLK~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_CLK,
	o => \CLK~input_o\);

-- Location: IOIBUF_X0_Y8_N15
\fsmc_wrn~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_wrn,
	o => \fsmc_wrn~input_o\);

-- Location: CLKCTRL_G0
\inst3|wr~clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst3|wr~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst3|wr~clkctrl_outclk\);

-- Location: CLKCTRL_G3
\CLK~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \CLK~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \CLK~inputclkctrl_outclk\);

-- Location: CLKCTRL_G1
\inst|wr~clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst|wr~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst|wr~clkctrl_outclk\);

-- Location: LCCOMB_X28_Y19_N26
\inst|ram_clk_limit[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[7]~feeder_combout\ = \inst|clk_para\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|clk_para\(7),
	combout => \inst|ram_clk_limit[7]~feeder_combout\);

-- Location: LCCOMB_X28_Y19_N12
\inst|ram_clk_limit[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[4]~feeder_combout\ = \inst|clk_para\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(4),
	combout => \inst|ram_clk_limit[4]~feeder_combout\);

-- Location: LCCOMB_X28_Y19_N22
\inst|ram_clk_limit[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[1]~feeder_combout\ = \inst|clk_para\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(1),
	combout => \inst|ram_clk_limit[1]~feeder_combout\);

-- Location: LCCOMB_X30_Y19_N26
\inst|addr_set[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[7]~feeder_combout\ = \inst3|outb\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst3|outb\(7),
	combout => \inst|addr_set[7]~feeder_combout\);

-- Location: LCCOMB_X30_Y19_N24
\inst|addr_set[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[6]~feeder_combout\ = \inst3|outb\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|outb\(6),
	combout => \inst|addr_set[6]~feeder_combout\);

-- Location: LCCOMB_X30_Y19_N14
\inst|addr_set[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[5]~feeder_combout\ = \inst3|outb\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|outb\(5),
	combout => \inst|addr_set[5]~feeder_combout\);

-- Location: LCCOMB_X30_Y19_N4
\inst|addr_set[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[4]~feeder_combout\ = \inst3|outb\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst3|outb\(4),
	combout => \inst|addr_set[4]~feeder_combout\);

-- Location: LCCOMB_X30_Y19_N18
\inst|addr_set[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[3]~feeder_combout\ = \inst3|outb\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst3|outb\(3),
	combout => \inst|addr_set[3]~feeder_combout\);

-- Location: LCCOMB_X26_Y19_N20
\inst3|outb[11]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[11]~feeder_combout\ = \fsmc_db[11]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[11]~input_o\,
	combout => \inst3|outb[11]~feeder_combout\);

-- Location: LCCOMB_X25_Y19_N6
\inst3|outa[10]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outa[10]~feeder_combout\ = \fsmc_db[10]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[10]~input_o\,
	combout => \inst3|outa[10]~feeder_combout\);

-- Location: LCCOMB_X26_Y19_N30
\inst3|outb[10]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[10]~feeder_combout\ = \fsmc_db[10]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[10]~input_o\,
	combout => \inst3|outb[10]~feeder_combout\);

-- Location: LCCOMB_X25_Y19_N26
\inst3|outa[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outa[7]~feeder_combout\ = \fsmc_db[7]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[7]~input_o\,
	combout => \inst3|outa[7]~feeder_combout\);

-- Location: IOOBUF_X5_Y0_N23
\c0~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_outclk\,
	devoe => ww_devoe,
	o => ww_c0);

-- Location: IOOBUF_X7_Y24_N9
\c1~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\,
	devoe => ww_devoe,
	o => ww_c1);

-- Location: IOOBUF_X7_Y0_N2
\c2~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk\,
	devoe => ww_devoe,
	o => ww_c2);

-- Location: IOOBUF_X1_Y0_N16
\locked~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|altpll_component|auto_generated|locked~combout\,
	devoe => ww_devoe,
	o => ww_locked);

-- Location: IOOBUF_X34_Y9_N23
\q[15]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(15),
	devoe => ww_devoe,
	o => ww_q(15));

-- Location: IOOBUF_X34_Y18_N2
\q[14]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(14),
	devoe => ww_devoe,
	o => ww_q(14));

-- Location: IOOBUF_X34_Y17_N2
\q[13]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(13),
	devoe => ww_devoe,
	o => ww_q(13));

-- Location: IOOBUF_X28_Y0_N2
\q[12]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(12),
	devoe => ww_devoe,
	o => ww_q(12));

-- Location: IOOBUF_X25_Y0_N2
\q[11]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(11),
	devoe => ww_devoe,
	o => ww_q(11));

-- Location: IOOBUF_X11_Y24_N16
\q[10]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(10),
	devoe => ww_devoe,
	o => ww_q(10));

-- Location: IOOBUF_X23_Y24_N9
\q[9]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(9),
	devoe => ww_devoe,
	o => ww_q(9));

-- Location: IOOBUF_X9_Y24_N9
\q[8]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(8),
	devoe => ww_devoe,
	o => ww_q(8));

-- Location: IOOBUF_X34_Y17_N23
\q[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(7),
	devoe => ww_devoe,
	o => ww_q(7));

-- Location: IOOBUF_X16_Y24_N9
\q[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(6),
	devoe => ww_devoe,
	o => ww_q(6));

-- Location: IOOBUF_X34_Y9_N2
\q[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(5),
	devoe => ww_devoe,
	o => ww_q(5));

-- Location: IOOBUF_X0_Y6_N16
\q[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(4),
	devoe => ww_devoe,
	o => ww_q(4));

-- Location: IOOBUF_X34_Y9_N9
\q[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(3),
	devoe => ww_devoe,
	o => ww_q(3));

-- Location: IOOBUF_X34_Y18_N16
\q[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(2),
	devoe => ww_devoe,
	o => ww_q(2));

-- Location: IOOBUF_X34_Y17_N16
\q[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(1),
	devoe => ww_devoe,
	o => ww_q(1));

-- Location: IOOBUF_X34_Y9_N16
\q[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1|altsyncram_component|auto_generated|q_a\(0),
	devoe => ww_devoe,
	o => ww_q(0));

-- Location: IOOBUF_X13_Y24_N16
\fsmc_db[15]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(15));

-- Location: IOOBUF_X18_Y24_N23
\fsmc_db[14]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(14));

-- Location: IOOBUF_X16_Y24_N16
\fsmc_db[13]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(13));

-- Location: IOOBUF_X34_Y19_N16
\fsmc_db[12]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(12));

-- Location: IOOBUF_X13_Y24_N23
\fsmc_db[11]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(11));

-- Location: IOOBUF_X23_Y24_N16
\fsmc_db[10]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(10));

-- Location: IOOBUF_X23_Y24_N2
\fsmc_db[9]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(9));

-- Location: IOOBUF_X18_Y24_N16
\fsmc_db[8]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(8));

-- Location: IOOBUF_X28_Y24_N16
\fsmc_db[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(7));

-- Location: IOOBUF_X34_Y20_N9
\fsmc_db[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(6));

-- Location: IOOBUF_X30_Y24_N2
\fsmc_db[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(5));

-- Location: IOOBUF_X28_Y24_N23
\fsmc_db[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(4));

-- Location: IOOBUF_X34_Y10_N9
\fsmc_db[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(3));

-- Location: IOOBUF_X28_Y24_N2
\fsmc_db[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(2));

-- Location: IOOBUF_X28_Y24_N9
\fsmc_db[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(1));

-- Location: IOOBUF_X30_Y24_N23
\fsmc_db[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	i => \inst3|rd~combout\,
	oe => VCC,
	devoe => ww_devoe,
	o => fsmc_db(0));

-- Location: IOIBUF_X0_Y9_N8
\fsmc_csn~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_csn,
	o => \fsmc_csn~input_o\);

-- Location: IOIBUF_X0_Y7_N1
\fsmc_rdn~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_rdn,
	o => \fsmc_rdn~input_o\);

-- Location: LCCOMB_X1_Y11_N18
\inst3|rd\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|rd~combout\ = LCELL((\fsmc_csn~input_o\ & \fsmc_rdn~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \fsmc_csn~input_o\,
	datad => \fsmc_rdn~input_o\,
	combout => \inst3|rd~combout\);

-- Location: IOIBUF_X0_Y11_N8
\inclk0~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_inclk0,
	o => \inclk0~input_o\);

-- Location: PLL_1
\inst2|altpll_component|auto_generated|pll1\ : cycloneive_pll
-- pragma translate_off
GENERIC MAP (
	auto_settings => "false",
	bandwidth_type => "medium",
	c0_high => 3,
	c0_initial => 1,
	c0_low => 3,
	c0_mode => "even",
	c0_ph => 0,
	c1_high => 6,
	c1_initial => 1,
	c1_low => 6,
	c1_mode => "even",
	c1_ph => 0,
	c1_use_casc_in => "off",
	c2_high => 2,
	c2_initial => 1,
	c2_low => 1,
	c2_mode => "odd",
	c2_ph => 0,
	c2_use_casc_in => "off",
	c3_high => 0,
	c3_initial => 0,
	c3_low => 0,
	c3_mode => "bypass",
	c3_ph => 0,
	c3_use_casc_in => "off",
	c4_high => 0,
	c4_initial => 0,
	c4_low => 0,
	c4_mode => "bypass",
	c4_ph => 0,
	c4_use_casc_in => "off",
	charge_pump_current_bits => 1,
	clk0_counter => "c0",
	clk0_divide_by => 1,
	clk0_duty_cycle => 50,
	clk0_multiply_by => 4,
	clk0_phase_shift => "0",
	clk1_counter => "c1",
	clk1_divide_by => 1,
	clk1_duty_cycle => 50,
	clk1_multiply_by => 2,
	clk1_phase_shift => "0",
	clk2_counter => "c2",
	clk2_divide_by => 1,
	clk2_duty_cycle => 50,
	clk2_multiply_by => 8,
	clk2_phase_shift => "0",
	clk3_counter => "unused",
	clk3_divide_by => 0,
	clk3_duty_cycle => 50,
	clk3_multiply_by => 0,
	clk3_phase_shift => "0",
	clk4_counter => "unused",
	clk4_divide_by => 0,
	clk4_duty_cycle => 50,
	clk4_multiply_by => 0,
	clk4_phase_shift => "0",
	compensate_clock => "clock0",
	inclk0_input_frequency => 40000,
	inclk1_input_frequency => 0,
	loop_filter_c_bits => 0,
	loop_filter_r_bits => 24,
	m => 24,
	m_initial => 1,
	m_ph => 0,
	n => 1,
	operation_mode => "normal",
	pfd_max => 200000,
	pfd_min => 3076,
	pll_compensation_delay => 6749,
	self_reset_on_loss_lock => "off",
	simulation_type => "timing",
	switch_over_type => "auto",
	vco_center => 1538,
	vco_divide_by => 0,
	vco_frequency_control => "auto",
	vco_max => 3333,
	vco_min => 1538,
	vco_multiply_by => 0,
	vco_phase_shift_step => 208,
	vco_post_scale => 2)
-- pragma translate_on
PORT MAP (
	areset => \areset~inputclkctrl_outclk\,
	fbin => \inst2|altpll_component|auto_generated|wire_pll1_fbout\,
	inclk => \inst2|altpll_component|auto_generated|pll1_INCLK_bus\,
	locked => \inst2|altpll_component|auto_generated|wire_pll1_locked\,
	fbout => \inst2|altpll_component|auto_generated|wire_pll1_fbout\,
	clk => \inst2|altpll_component|auto_generated|pll1_CLK_bus\);

-- Location: CLKCTRL_PLL1E0
\inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "external clock output",
	ena_register_mode => "double register")
-- pragma translate_on
PORT MAP (
	inclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_e_c0_outclk\);

-- Location: CLKCTRL_G4
\inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\);

-- Location: CLKCTRL_G2
\inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst2|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk\);

-- Location: LCCOMB_X1_Y1_N0
\inst2|altpll_component|auto_generated|pll_lock_sync~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst2|altpll_component|auto_generated|pll_lock_sync~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \inst2|altpll_component|auto_generated|pll_lock_sync~feeder_combout\);

-- Location: IOIBUF_X34_Y12_N22
\areset~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_areset,
	o => \areset~input_o\);

-- Location: CLKCTRL_G5
\areset~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \areset~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \areset~inputclkctrl_outclk\);

-- Location: FF_X1_Y1_N1
\inst2|altpll_component|auto_generated|pll_lock_sync\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst2|altpll_component|auto_generated|wire_pll1_locked\,
	d => \inst2|altpll_component|auto_generated|pll_lock_sync~feeder_combout\,
	clrn => \ALT_INV_areset~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst2|altpll_component|auto_generated|pll_lock_sync~q\);

-- Location: LCCOMB_X1_Y1_N26
\inst2|altpll_component|auto_generated|locked\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst2|altpll_component|auto_generated|locked~combout\ = (\inst2|altpll_component|auto_generated|wire_pll1_locked\ & \inst2|altpll_component|auto_generated|pll_lock_sync~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst2|altpll_component|auto_generated|wire_pll1_locked\,
	datad => \inst2|altpll_component|auto_generated|pll_lock_sync~q\,
	combout => \inst2|altpll_component|auto_generated|locked~combout\);

-- Location: IOIBUF_X0_Y11_N22
\fsmc_ab[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_ab(0),
	o => \fsmc_ab[0]~input_o\);

-- Location: LCCOMB_X29_Y19_N16
\inst|ram_wr_flag~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_wr_flag~0_combout\ = !\fsmc_ab[0]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_ab[0]~input_o\,
	combout => \inst|ram_wr_flag~0_combout\);

-- Location: IOIBUF_X34_Y12_N15
\fsmc_resetn~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_resetn,
	o => \fsmc_resetn~input_o\);

-- Location: CLKCTRL_G9
\fsmc_resetn~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \fsmc_resetn~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \fsmc_resetn~inputclkctrl_outclk\);

-- Location: FF_X29_Y19_N17
\inst|ram_wr_flag\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_wr_flag~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_wr_flag~q\);

-- Location: LCCOMB_X26_Y17_N20
\inst|RAM_WEN~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_WEN~0_combout\ = (\inst|ram_clk_div~q\ & (\inst|ram_wr_flag~q\)) # (!\inst|ram_clk_div~q\ & ((\inst|RAM_WEN~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100011011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_div~q\,
	datab => \inst|ram_wr_flag~q\,
	datac => \inst|RAM_WEN~q\,
	combout => \inst|RAM_WEN~0_combout\);

-- Location: FF_X26_Y17_N21
\inst|RAM_WEN\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_WEN~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_WEN~q\);

-- Location: LCCOMB_X28_Y17_N30
\inst|ram_clk_div~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_div~0_combout\ = !\inst|ram_clk_div~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|ram_clk_div~q\,
	combout => \inst|ram_clk_div~0_combout\);

-- Location: FF_X28_Y17_N31
\inst|ram_clk_div\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_div~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_div~q\);

-- Location: LCCOMB_X33_Y12_N16
\inst|RAM_CLK~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_CLK~feeder_combout\ = \inst|ram_clk_div~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|ram_clk_div~q\,
	combout => \inst|RAM_CLK~feeder_combout\);

-- Location: FF_X33_Y12_N17
\inst|RAM_CLK\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_CLK~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_CLK~q\);

-- Location: CLKCTRL_G8
\inst|RAM_CLK~clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \inst|RAM_CLK~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \inst|RAM_CLK~clkctrl_outclk\);

-- Location: IOIBUF_X30_Y24_N22
\fsmc_db[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(0),
	o => \fsmc_db[0]~input_o\);

-- Location: IOIBUF_X16_Y24_N1
\fsmc_ab[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_ab(1),
	o => \fsmc_ab[1]~input_o\);

-- Location: IOIBUF_X16_Y24_N22
\fsmc_ab[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_fsmc_ab(2),
	o => \fsmc_ab[2]~input_o\);

-- Location: LCCOMB_X24_Y19_N0
\inst3|Decoder0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|Decoder0~1_combout\ = (!\fsmc_ab[1]~input_o\ & (!\fsmc_ab[2]~input_o\ & !\fsmc_ab[0]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \fsmc_ab[1]~input_o\,
	datac => \fsmc_ab[2]~input_o\,
	datad => \fsmc_ab[0]~input_o\,
	combout => \inst3|Decoder0~1_combout\);

-- Location: FF_X24_Y19_N25
\inst3|outa[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[0]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(0));

-- Location: IOIBUF_X16_Y24_N15
\fsmc_db[13]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(13),
	o => \fsmc_db[13]~input_o\);

-- Location: FF_X25_Y19_N9
\inst3|outa[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[13]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(13));

-- Location: IOIBUF_X34_Y19_N15
\fsmc_db[12]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(12),
	o => \fsmc_db[12]~input_o\);

-- Location: FF_X25_Y19_N3
\inst3|outa[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[12]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(12));

-- Location: IOIBUF_X18_Y24_N22
\fsmc_db[14]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(14),
	o => \fsmc_db[14]~input_o\);

-- Location: FF_X26_Y19_N29
\inst3|outa[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[14]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(14));

-- Location: LCCOMB_X25_Y19_N2
\inst|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~0_combout\ = (!\inst3|outa\(15) & (!\inst3|outa\(13) & (!\inst3|outa\(12) & !\inst3|outa\(14))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(15),
	datab => \inst3|outa\(13),
	datac => \inst3|outa\(12),
	datad => \inst3|outa\(14),
	combout => \inst|Equal0~0_combout\);

-- Location: IOIBUF_X34_Y10_N8
\fsmc_db[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(3),
	o => \fsmc_db[3]~input_o\);

-- Location: FF_X25_Y19_N19
\inst3|outa[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[3]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(3));

-- Location: IOIBUF_X34_Y20_N8
\fsmc_db[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(6),
	o => \fsmc_db[6]~input_o\);

-- Location: FF_X26_Y19_N25
\inst3|outa[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[6]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(6));

-- Location: IOIBUF_X28_Y24_N22
\fsmc_db[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(4),
	o => \fsmc_db[4]~input_o\);

-- Location: FF_X25_Y19_N21
\inst3|outa[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[4]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(4));

-- Location: IOIBUF_X30_Y24_N1
\fsmc_db[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(5),
	o => \fsmc_db[5]~input_o\);

-- Location: FF_X26_Y19_N19
\inst3|outa[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[5]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(5));

-- Location: LCCOMB_X25_Y19_N20
\inst|Equal0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~2_combout\ = (!\inst3|outa\(7) & (!\inst3|outa\(6) & (!\inst3|outa\(4) & !\inst3|outa\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(7),
	datab => \inst3|outa\(6),
	datac => \inst3|outa\(4),
	datad => \inst3|outa\(5),
	combout => \inst|Equal0~2_combout\);

-- Location: LCCOMB_X25_Y19_N18
\inst|Equal0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~3_combout\ = (\inst|Equal0~1_combout\ & (\inst|Equal0~0_combout\ & (!\inst3|outa\(3) & \inst|Equal0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal0~1_combout\,
	datab => \inst|Equal0~0_combout\,
	datac => \inst3|outa\(3),
	datad => \inst|Equal0~2_combout\,
	combout => \inst|Equal0~3_combout\);

-- Location: IOIBUF_X28_Y24_N8
\fsmc_db[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(1),
	o => \fsmc_db[1]~input_o\);

-- Location: FF_X25_Y19_N15
\inst3|outa[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[1]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(1));

-- Location: IOIBUF_X13_Y24_N22
\fsmc_db[11]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(11),
	o => \fsmc_db[11]~input_o\);

-- Location: FF_X25_Y19_N5
\inst3|outa[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[11]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(11));

-- Location: IOIBUF_X18_Y24_N15
\fsmc_db[8]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(8),
	o => \fsmc_db[8]~input_o\);

-- Location: FF_X25_Y19_N25
\inst3|outa[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[8]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(8));

-- Location: IOIBUF_X23_Y24_N1
\fsmc_db[9]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(9),
	o => \fsmc_db[9]~input_o\);

-- Location: LCCOMB_X26_Y19_N22
\inst3|outa[9]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outa[9]~feeder_combout\ = \fsmc_db[9]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[9]~input_o\,
	combout => \inst3|outa[9]~feeder_combout\);

-- Location: FF_X26_Y19_N23
\inst3|outa[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outa[9]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(9));

-- Location: LCCOMB_X25_Y19_N24
\inst|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~1_combout\ = (!\inst3|outa\(10) & (!\inst3|outa\(11) & (!\inst3|outa\(8) & !\inst3|outa\(9))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(10),
	datab => \inst3|outa\(11),
	datac => \inst3|outa\(8),
	datad => \inst3|outa\(9),
	combout => \inst|Equal0~1_combout\);

-- Location: LCCOMB_X25_Y19_N12
\inst|Equal4~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal4~1_combout\ = (\inst|Equal4~0_combout\ & (\inst|Equal0~0_combout\ & (\inst|Equal0~1_combout\ & \inst|Equal0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal4~0_combout\,
	datab => \inst|Equal0~0_combout\,
	datac => \inst|Equal0~1_combout\,
	datad => \inst|Equal0~2_combout\,
	combout => \inst|Equal4~1_combout\);

-- Location: LCCOMB_X25_Y19_N30
\inst|Selector2~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector2~5_combout\ = (!\inst|Equal4~1_combout\ & (((\inst3|outa\(2) & !\inst3|outa\(1))) # (!\inst|Equal0~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(2),
	datab => \inst|Equal0~3_combout\,
	datac => \inst3|outa\(1),
	datad => \inst|Equal4~1_combout\,
	combout => \inst|Selector2~5_combout\);

-- Location: LCCOMB_X25_Y19_N28
\inst|Selector4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector4~0_combout\ = (\inst|Equal5~0_combout\ & (((\inst|ddsSta.WR_ONE_BYTE~q\ & \inst|Selector2~5_combout\)) # (!\inst3|outa\(0)))) # (!\inst|Equal5~0_combout\ & (((\inst|ddsSta.WR_ONE_BYTE~q\ & \inst|Selector2~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal5~0_combout\,
	datab => \inst3|outa\(0),
	datac => \inst|ddsSta.WR_ONE_BYTE~q\,
	datad => \inst|Selector2~5_combout\,
	combout => \inst|Selector4~0_combout\);

-- Location: FF_X25_Y19_N29
\inst|ddsSta.WR_ONE_BYTE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector4~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ddsSta.WR_ONE_BYTE~q\);

-- Location: LCCOMB_X24_Y19_N22
\inst3|Decoder0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|Decoder0~0_combout\ = (!\fsmc_ab[1]~input_o\ & (!\fsmc_ab[2]~input_o\ & \fsmc_ab[0]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \fsmc_ab[1]~input_o\,
	datac => \fsmc_ab[2]~input_o\,
	datad => \fsmc_ab[0]~input_o\,
	combout => \inst3|Decoder0~0_combout\);

-- Location: FF_X30_Y17_N29
\inst3|outb[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[0]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(0));

-- Location: LCCOMB_X25_Y17_N12
\inst|Selector24~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector24~0_combout\ = (\inst|WideOr11~0_combout\ & ((\inst|dds_ram_data\(0)) # ((\inst|ddsSta.WR_ONE_BYTE~q\ & \inst3|outb\(0))))) # (!\inst|WideOr11~0_combout\ & (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|WideOr11~0_combout\,
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(0),
	datad => \inst3|outb\(0),
	combout => \inst|Selector24~0_combout\);

-- Location: FF_X25_Y17_N13
\inst|dds_ram_data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector24~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(0));

-- Location: LCCOMB_X26_Y17_N10
\inst|RAM_DAT[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[0]~feeder_combout\ = \inst|dds_ram_data\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(0),
	combout => \inst|RAM_DAT[0]~feeder_combout\);

-- Location: LCCOMB_X26_Y17_N22
\inst|RAM_DAT[15]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[15]~0_combout\ = (\inst|ram_clk_div~q\ & (\inst|ddsSta.WR_ONE_BYTE~q\ & \inst|ram_wr_flag~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_div~q\,
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datad => \inst|ram_wr_flag~q\,
	combout => \inst|RAM_DAT[15]~0_combout\);

-- Location: FF_X26_Y17_N11
\inst|RAM_DAT[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[0]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(0));

-- Location: LCCOMB_X25_Y19_N10
\inst|Selector7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector7~0_combout\ = (\inst|Equal4~1_combout\ & ((\inst3|outa\(0)) # ((\inst|ddsSta.SET_ADDR~q\ & \inst|Selector2~5_combout\)))) # (!\inst|Equal4~1_combout\ & (((\inst|ddsSta.SET_ADDR~q\ & \inst|Selector2~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal4~1_combout\,
	datab => \inst3|outa\(0),
	datac => \inst|ddsSta.SET_ADDR~q\,
	datad => \inst|Selector2~5_combout\,
	combout => \inst|Selector7~0_combout\);

-- Location: FF_X25_Y19_N11
\inst|ddsSta.SET_ADDR\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector7~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ddsSta.SET_ADDR~q\);

-- Location: LCCOMB_X30_Y19_N28
\inst|addr_set[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[0]~0_combout\ = (!\fsmc_ab[0]~input_o\ & \inst|ddsSta.SET_ADDR~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_ab[0]~input_o\,
	datad => \inst|ddsSta.SET_ADDR~q\,
	combout => \inst|addr_set[0]~0_combout\);

-- Location: FF_X30_Y19_N29
\inst|addr_set[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	asdata => \inst3|outb\(0),
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(0));

-- Location: FF_X30_Y17_N23
\inst3|outb[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[6]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(6));

-- Location: LCCOMB_X29_Y19_N22
\inst|clk_para[6]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[6]~3_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & ((\inst|clk_para\(6)))) # (!\fsmc_ab[0]~input_o\ & (\inst3|outb\(6))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(6)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \inst3|outb\(6),
	datac => \inst|clk_para\(6),
	datad => \fsmc_ab[0]~input_o\,
	combout => \inst|clk_para[6]~3_combout\);

-- Location: FF_X29_Y19_N23
\inst|clk_para[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[6]~3_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(6));

-- Location: LCCOMB_X28_Y19_N0
\inst|ram_clk_limit[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[6]~feeder_combout\ = \inst|clk_para\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(6),
	combout => \inst|ram_clk_limit[6]~feeder_combout\);

-- Location: LCCOMB_X25_Y19_N0
\inst|Selector5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector5~0_combout\ = (\inst|Equal5~0_combout\ & ((\inst3|outa\(0)) # ((\inst|ddsSta.SET_FRE_RANGE~q\ & \inst|Selector2~5_combout\)))) # (!\inst|Equal5~0_combout\ & (((\inst|ddsSta.SET_FRE_RANGE~q\ & \inst|Selector2~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal5~0_combout\,
	datab => \inst3|outa\(0),
	datac => \inst|ddsSta.SET_FRE_RANGE~q\,
	datad => \inst|Selector2~5_combout\,
	combout => \inst|Selector5~0_combout\);

-- Location: FF_X25_Y19_N1
\inst|ddsSta.SET_FRE_RANGE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector5~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ddsSta.SET_FRE_RANGE~q\);

-- Location: IOIBUF_X28_Y24_N1
\fsmc_db[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(2),
	o => \fsmc_db[2]~input_o\);

-- Location: FF_X25_Y19_N17
\inst3|outa[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	asdata => \fsmc_db[2]~input_o\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst3|Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outa\(2));

-- Location: LCCOMB_X25_Y19_N16
\inst|Equal5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal5~0_combout\ = (\inst3|outa\(1) & (\inst3|outa\(2) & \inst|Equal0~3_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(1),
	datac => \inst3|outa\(2),
	datad => \inst|Equal0~3_combout\,
	combout => \inst|Equal5~0_combout\);

-- Location: LCCOMB_X24_Y19_N10
\inst|always0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|always0~0_combout\ = (!\inst3|outa\(2) & \inst|Equal0~3_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst3|outa\(2),
	datad => \inst|Equal0~3_combout\,
	combout => \inst|always0~0_combout\);

-- Location: LCCOMB_X24_Y19_N24
\inst|always0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|always0~1_combout\ = (\inst|Equal5~0_combout\) # ((\inst|always0~0_combout\) # ((\inst|Equal4~1_combout\ & \inst3|outa\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Equal4~1_combout\,
	datab => \inst|Equal5~0_combout\,
	datac => \inst3|outa\(0),
	datad => \inst|always0~0_combout\,
	combout => \inst|always0~1_combout\);

-- Location: LCCOMB_X24_Y19_N18
\inst|ddsSta~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ddsSta~20_combout\ = (!\inst|always0~1_combout\ & ((\inst|ddsSta.SET_FRE_PARA~q\) # ((!\inst3|outa\(0) & \inst|Equal4~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(0),
	datab => \inst|Equal4~1_combout\,
	datac => \inst|ddsSta.SET_FRE_PARA~q\,
	datad => \inst|always0~1_combout\,
	combout => \inst|ddsSta~20_combout\);

-- Location: FF_X24_Y19_N19
\inst|ddsSta.SET_FRE_PARA\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ddsSta~20_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ddsSta.SET_FRE_PARA~q\);

-- Location: LCCOMB_X30_Y17_N0
\inst3|outb[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[1]~feeder_combout\ = \fsmc_db[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[1]~input_o\,
	combout => \inst3|outb[1]~feeder_combout\);

-- Location: FF_X30_Y17_N1
\inst3|outb[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[1]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(1));

-- Location: LCCOMB_X29_Y19_N14
\inst|clk_range[1]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_range[1]~0_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_range\(1))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_RANGE~q\ & ((\inst3|outb\(1)))) # (!\inst|ddsSta.SET_FRE_RANGE~q\ & (\inst|clk_range\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_ab[0]~input_o\,
	datab => \inst|ddsSta.SET_FRE_RANGE~q\,
	datac => \inst|clk_range\(1),
	datad => \inst3|outb\(1),
	combout => \inst|clk_range[1]~0_combout\);

-- Location: FF_X29_Y19_N15
\inst|clk_range[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_range[1]~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_range\(1));

-- Location: LCCOMB_X29_Y19_N4
\inst|clk_range[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_range[0]~1_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_range\(0))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_RANGE~q\ & ((\inst3|outb\(0)))) # (!\inst|ddsSta.SET_FRE_RANGE~q\ & (\inst|clk_range\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_ab[0]~input_o\,
	datab => \inst|ddsSta.SET_FRE_RANGE~q\,
	datac => \inst|clk_range\(0),
	datad => \inst3|outb\(0),
	combout => \inst|clk_range[0]~1_combout\);

-- Location: FF_X29_Y19_N5
\inst|clk_range[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_range[0]~1_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_range\(0));

-- Location: LCCOMB_X28_Y19_N28
\inst|ram_clk_limit[9]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[9]~0_combout\ = (\inst|ram_clk_div~q\ & (\inst|ram_wr_flag~q\ & ((!\inst|clk_range\(0)) # (!\inst|clk_range\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_div~q\,
	datab => \inst|clk_range\(1),
	datac => \inst|ram_wr_flag~q\,
	datad => \inst|clk_range\(0),
	combout => \inst|ram_clk_limit[9]~0_combout\);

-- Location: LCCOMB_X28_Y19_N30
\inst|ram_clk_limit[9]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[9]~1_combout\ = (\inst|ram_clk_limit[9]~0_combout\ & ((\inst|ddsSta.SET_FRE_RANGE~q\) # (\inst|ddsSta.SET_FRE_PARA~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|ddsSta.SET_FRE_RANGE~q\,
	datac => \inst|ddsSta.SET_FRE_PARA~q\,
	datad => \inst|ram_clk_limit[9]~0_combout\,
	combout => \inst|ram_clk_limit[9]~1_combout\);

-- Location: FF_X28_Y19_N1
\inst|ram_clk_limit[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[6]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(6));

-- Location: LCCOMB_X29_Y19_N30
\inst|clk_para[3]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[3]~6_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_para\(3))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_PARA~q\ & (\inst3|outb\(3))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & ((\inst|clk_para\(3))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110001011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(3),
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(3),
	datad => \inst|ddsSta.SET_FRE_PARA~q\,
	combout => \inst|clk_para[3]~6_combout\);

-- Location: FF_X29_Y19_N31
\inst|clk_para[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[3]~6_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(3));

-- Location: FF_X28_Y19_N19
\inst|ram_clk_limit[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	asdata => \inst|clk_para\(3),
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(3));

-- Location: LCCOMB_X30_Y17_N4
\inst3|outb[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[5]~feeder_combout\ = \fsmc_db[5]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[5]~input_o\,
	combout => \inst3|outb[5]~feeder_combout\);

-- Location: FF_X30_Y17_N5
\inst3|outb[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[5]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(5));

-- Location: LCCOMB_X29_Y19_N28
\inst|clk_para[5]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[5]~4_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & (\inst|clk_para\(5))) # (!\fsmc_ab[0]~input_o\ & ((\inst3|outb\(5)))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(5)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(5),
	datad => \inst3|outb\(5),
	combout => \inst|clk_para[5]~4_combout\);

-- Location: FF_X29_Y19_N29
\inst|clk_para[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[5]~4_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(5));

-- Location: LCCOMB_X28_Y19_N10
\inst|ram_clk_limit[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[5]~feeder_combout\ = \inst|clk_para\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(5),
	combout => \inst|ram_clk_limit[5]~feeder_combout\);

-- Location: FF_X28_Y19_N11
\inst|ram_clk_limit[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[5]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(5));

-- Location: LCCOMB_X28_Y19_N18
\inst|RAM_ADDR[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~1_combout\ = (!\inst|ram_clk_limit\(4) & (!\inst|ram_clk_limit\(6) & (!\inst|ram_clk_limit\(3) & !\inst|ram_clk_limit\(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_limit\(4),
	datab => \inst|ram_clk_limit\(6),
	datac => \inst|ram_clk_limit\(3),
	datad => \inst|ram_clk_limit\(5),
	combout => \inst|RAM_ADDR[0]~1_combout\);

-- Location: LCCOMB_X30_Y17_N30
\inst3|outb[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[2]~feeder_combout\ = \fsmc_db[2]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[2]~input_o\,
	combout => \inst3|outb[2]~feeder_combout\);

-- Location: FF_X30_Y17_N31
\inst3|outb[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[2]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(2));

-- Location: LCCOMB_X29_Y19_N8
\inst|clk_para[2]~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[2]~7_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_para\(2))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_PARA~q\ & (\inst3|outb\(2))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & ((\inst|clk_para\(2))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110010011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_ab[0]~input_o\,
	datab => \inst3|outb\(2),
	datac => \inst|clk_para\(2),
	datad => \inst|ddsSta.SET_FRE_PARA~q\,
	combout => \inst|clk_para[2]~7_combout\);

-- Location: FF_X29_Y19_N9
\inst|clk_para[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[2]~7_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(2));

-- Location: FF_X28_Y19_N5
\inst|ram_clk_limit[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	asdata => \inst|clk_para\(2),
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(2));

-- Location: LCCOMB_X25_Y17_N28
\inst|clk_para[0]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[0]~9_combout\ = (\fsmc_ab[0]~input_o\ & (((\inst|clk_para\(0))))) # (!\fsmc_ab[0]~input_o\ & ((\inst|ddsSta.SET_FRE_PARA~q\ & ((\inst3|outb\(0)))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (\inst|clk_para\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_ab[0]~input_o\,
	datab => \inst|ddsSta.SET_FRE_PARA~q\,
	datac => \inst|clk_para\(0),
	datad => \inst3|outb\(0),
	combout => \inst|clk_para[0]~9_combout\);

-- Location: FF_X25_Y17_N29
\inst|clk_para[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[0]~9_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(0));

-- Location: LCCOMB_X28_Y19_N24
\inst|ram_clk_limit[0]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[0]~feeder_combout\ = \inst|clk_para\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(0),
	combout => \inst|ram_clk_limit[0]~feeder_combout\);

-- Location: FF_X28_Y19_N25
\inst|ram_clk_limit[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[0]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(0));

-- Location: LCCOMB_X28_Y19_N4
\inst|RAM_ADDR[0]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~2_combout\ = (!\inst|ram_clk_limit\(1) & (!\inst|ram_clk_limit\(2) & !\inst|ram_clk_limit\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_limit\(1),
	datac => \inst|ram_clk_limit\(2),
	datad => \inst|ram_clk_limit\(0),
	combout => \inst|RAM_ADDR[0]~2_combout\);

-- Location: LCCOMB_X26_Y19_N10
\inst3|outb[8]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[8]~feeder_combout\ = \fsmc_db[8]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[8]~input_o\,
	combout => \inst3|outb[8]~feeder_combout\);

-- Location: FF_X26_Y19_N11
\inst3|outb[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[8]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(8));

-- Location: LCCOMB_X29_Y19_N26
\inst|clk_para[8]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[8]~1_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & (\inst|clk_para\(8))) # (!\fsmc_ab[0]~input_o\ & ((\inst3|outb\(8)))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(8)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(8),
	datad => \inst3|outb\(8),
	combout => \inst|clk_para[8]~1_combout\);

-- Location: FF_X29_Y19_N27
\inst|clk_para[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[8]~1_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(8));

-- Location: LCCOMB_X28_Y19_N16
\inst|ram_clk_limit[8]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_clk_limit[8]~feeder_combout\ = \inst|clk_para\(8)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|clk_para\(8),
	combout => \inst|ram_clk_limit[8]~feeder_combout\);

-- Location: FF_X28_Y19_N17
\inst|ram_clk_limit[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|ram_clk_limit[8]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(8));

-- Location: LCCOMB_X26_Y19_N16
\inst3|outb[9]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[9]~feeder_combout\ = \fsmc_db[9]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[9]~input_o\,
	combout => \inst3|outb[9]~feeder_combout\);

-- Location: FF_X26_Y19_N17
\inst3|outb[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[9]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(9));

-- Location: LCCOMB_X29_Y19_N12
\inst|clk_para[9]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|clk_para[9]~0_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\ & ((\fsmc_ab[0]~input_o\ & (\inst|clk_para\(9))) # (!\fsmc_ab[0]~input_o\ & ((\inst3|outb\(9)))))) # (!\inst|ddsSta.SET_FRE_PARA~q\ & (((\inst|clk_para\(9)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \fsmc_ab[0]~input_o\,
	datac => \inst|clk_para\(9),
	datad => \inst3|outb\(9),
	combout => \inst|clk_para[9]~0_combout\);

-- Location: FF_X29_Y19_N13
\inst|clk_para[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|clk_para[9]~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|clk_para\(9));

-- Location: FF_X28_Y19_N7
\inst|ram_clk_limit[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	asdata => \inst|clk_para\(9),
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst|ram_clk_limit[9]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_clk_limit\(9));

-- Location: LCCOMB_X24_Y19_N4
\inst|Selector8~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector8~2_combout\ = (\inst|Selector8~1_combout\) # ((\inst|dds_out_en~q\ & ((\inst|Equal4~1_combout\) # (!\inst|always0~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110101011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Selector8~1_combout\,
	datab => \inst|Equal4~1_combout\,
	datac => \inst|dds_out_en~q\,
	datad => \inst|always0~1_combout\,
	combout => \inst|Selector8~2_combout\);

-- Location: FF_X24_Y19_N5
\inst|dds_out_en\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector8~2_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_out_en~q\);

-- Location: LCCOMB_X28_Y19_N6
\inst|RAM_ADDR[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~0_combout\ = (!\inst|ram_clk_limit\(7) & (!\inst|ram_clk_limit\(8) & (!\inst|ram_clk_limit\(9) & \inst|dds_out_en~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_limit\(7),
	datab => \inst|ram_clk_limit\(8),
	datac => \inst|ram_clk_limit\(9),
	datad => \inst|dds_out_en~q\,
	combout => \inst|RAM_ADDR[0]~0_combout\);

-- Location: LCCOMB_X28_Y19_N14
\inst|RAM_ADDR[0]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~3_combout\ = (\inst|ram_wr_flag~q\) # (((!\inst|RAM_ADDR[0]~0_combout\) # (!\inst|RAM_ADDR[0]~2_combout\)) # (!\inst|RAM_ADDR[0]~1_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_wr_flag~q\,
	datab => \inst|RAM_ADDR[0]~1_combout\,
	datac => \inst|RAM_ADDR[0]~2_combout\,
	datad => \inst|RAM_ADDR[0]~0_combout\,
	combout => \inst|RAM_ADDR[0]~3_combout\);

-- Location: LCCOMB_X30_Y19_N8
\inst|addr_set[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[2]~feeder_combout\ = \inst3|outb\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|outb\(2),
	combout => \inst|addr_set[2]~feeder_combout\);

-- Location: FF_X30_Y19_N9
\inst|addr_set[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[2]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(2));

-- Location: LCCOMB_X28_Y17_N16
\inst|Add1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~4_combout\ = (\inst|RAM_ADDR\(2) & (\inst|Add1~3\ $ (GND))) # (!\inst|RAM_ADDR\(2) & (!\inst|Add1~3\ & VCC))
-- \inst|Add1~5\ = CARRY((\inst|RAM_ADDR\(2) & !\inst|Add1~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|RAM_ADDR\(2),
	datad => VCC,
	cin => \inst|Add1~3\,
	combout => \inst|Add1~4_combout\,
	cout => \inst|Add1~5\);

-- Location: LCCOMB_X29_Y17_N8
\inst|RAM_ADDR~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~8_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (((\inst|addr_set\(2))))) # (!\inst|RAM_ADDR[0]~3_combout\ & (!\inst|LessThan1~14_combout\ & ((\inst|Add1~4_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|LessThan1~14_combout\,
	datab => \inst|addr_set\(2),
	datac => \inst|Add1~4_combout\,
	datad => \inst|RAM_ADDR[0]~3_combout\,
	combout => \inst|RAM_ADDR~8_combout\);

-- Location: LCCOMB_X28_Y19_N20
\inst|RAM_ADDR[0]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~5_combout\ = (\inst|RAM_ADDR[0]~1_combout\ & (\inst|RAM_ADDR[0]~2_combout\ & \inst|RAM_ADDR[0]~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|RAM_ADDR[0]~1_combout\,
	datac => \inst|RAM_ADDR[0]~2_combout\,
	datad => \inst|RAM_ADDR[0]~0_combout\,
	combout => \inst|RAM_ADDR[0]~5_combout\);

-- Location: LCCOMB_X28_Y19_N2
\inst|RAM_ADDR[0]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR[0]~6_combout\ = (\inst|ram_clk_div~q\ & ((\inst|ram_wr_flag~q\ & (\inst|ddsSta.SET_ADDR~q\)) # (!\inst|ram_wr_flag~q\ & ((\inst|RAM_ADDR[0]~5_combout\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010001010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_clk_div~q\,
	datab => \inst|ram_wr_flag~q\,
	datac => \inst|ddsSta.SET_ADDR~q\,
	datad => \inst|RAM_ADDR[0]~5_combout\,
	combout => \inst|RAM_ADDR[0]~6_combout\);

-- Location: FF_X29_Y17_N9
\inst|RAM_ADDR[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~8_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(2));

-- Location: LCCOMB_X28_Y17_N18
\inst|Add1~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~6_combout\ = (\inst|RAM_ADDR\(3) & (!\inst|Add1~5\)) # (!\inst|RAM_ADDR\(3) & ((\inst|Add1~5\) # (GND)))
-- \inst|Add1~7\ = CARRY((!\inst|Add1~5\) # (!\inst|RAM_ADDR\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(3),
	datad => VCC,
	cin => \inst|Add1~5\,
	combout => \inst|Add1~6_combout\,
	cout => \inst|Add1~7\);

-- Location: LCCOMB_X28_Y17_N20
\inst|Add1~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~8_combout\ = (\inst|RAM_ADDR\(4) & (\inst|Add1~7\ $ (GND))) # (!\inst|RAM_ADDR\(4) & (!\inst|Add1~7\ & VCC))
-- \inst|Add1~9\ = CARRY((\inst|RAM_ADDR\(4) & !\inst|Add1~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|RAM_ADDR\(4),
	datad => VCC,
	cin => \inst|Add1~7\,
	combout => \inst|Add1~8_combout\,
	cout => \inst|Add1~9\);

-- Location: LCCOMB_X29_Y17_N0
\inst|RAM_ADDR~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~10_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (\inst|addr_set\(4))) # (!\inst|RAM_ADDR[0]~3_combout\ & (((!\inst|LessThan1~14_combout\ & \inst|Add1~8_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|addr_set\(4),
	datab => \inst|RAM_ADDR[0]~3_combout\,
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|Add1~8_combout\,
	combout => \inst|RAM_ADDR~10_combout\);

-- Location: FF_X29_Y17_N1
\inst|RAM_ADDR[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~10_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(4));

-- Location: LCCOMB_X28_Y17_N22
\inst|Add1~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~10_combout\ = (\inst|RAM_ADDR\(5) & (!\inst|Add1~9\)) # (!\inst|RAM_ADDR\(5) & ((\inst|Add1~9\) # (GND)))
-- \inst|Add1~11\ = CARRY((!\inst|Add1~9\) # (!\inst|RAM_ADDR\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(5),
	datad => VCC,
	cin => \inst|Add1~9\,
	combout => \inst|Add1~10_combout\,
	cout => \inst|Add1~11\);

-- Location: LCCOMB_X28_Y17_N24
\inst|Add1~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~12_combout\ = (\inst|RAM_ADDR\(6) & (\inst|Add1~11\ $ (GND))) # (!\inst|RAM_ADDR\(6) & (!\inst|Add1~11\ & VCC))
-- \inst|Add1~13\ = CARRY((\inst|RAM_ADDR\(6) & !\inst|Add1~11\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(6),
	datad => VCC,
	cin => \inst|Add1~11\,
	combout => \inst|Add1~12_combout\,
	cout => \inst|Add1~13\);

-- Location: LCCOMB_X28_Y17_N26
\inst|Add1~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Add1~14_combout\ = \inst|Add1~13\ $ (\inst|RAM_ADDR\(7))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \inst|RAM_ADDR\(7),
	cin => \inst|Add1~13\,
	combout => \inst|Add1~14_combout\);

-- Location: LCCOMB_X28_Y19_N8
\inst|RAM_ADDR~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~13_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (\inst|addr_set\(7))) # (!\inst|RAM_ADDR[0]~3_combout\ & (((!\inst|LessThan1~14_combout\ & \inst|Add1~14_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|addr_set\(7),
	datab => \inst|RAM_ADDR[0]~3_combout\,
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|Add1~14_combout\,
	combout => \inst|RAM_ADDR~13_combout\);

-- Location: FF_X28_Y19_N9
\inst|RAM_ADDR[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~13_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(7));

-- Location: IOIBUF_X28_Y24_N15
\fsmc_db[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => fsmc_db(7),
	o => \fsmc_db[7]~input_o\);

-- Location: LCCOMB_X30_Y19_N12
\inst3|outb[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[7]~feeder_combout\ = \fsmc_db[7]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[7]~input_o\,
	combout => \inst3|outb[7]~feeder_combout\);

-- Location: FF_X30_Y19_N13
\inst3|outb[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[7]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(7));

-- Location: LCCOMB_X30_Y17_N24
\inst3|outb[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[3]~feeder_combout\ = \fsmc_db[3]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[3]~input_o\,
	combout => \inst3|outb[3]~feeder_combout\);

-- Location: FF_X30_Y17_N25
\inst3|outb[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[3]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(3));

-- Location: LCCOMB_X30_Y17_N6
\inst|ram_buf_size[1]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[1]~8_cout\ = CARRY(\inst3|outb\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst3|outb\(0),
	datad => VCC,
	cout => \inst|ram_buf_size[1]~8_cout\);

-- Location: LCCOMB_X30_Y17_N8
\inst|ram_buf_size[1]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[1]~9_combout\ = (\inst3|outb\(1) & (\inst|ram_buf_size[1]~8_cout\ & VCC)) # (!\inst3|outb\(1) & (!\inst|ram_buf_size[1]~8_cout\))
-- \inst|ram_buf_size[1]~10\ = CARRY((!\inst3|outb\(1) & !\inst|ram_buf_size[1]~8_cout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100000011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst3|outb\(1),
	datad => VCC,
	cin => \inst|ram_buf_size[1]~8_cout\,
	combout => \inst|ram_buf_size[1]~9_combout\,
	cout => \inst|ram_buf_size[1]~10\);

-- Location: LCCOMB_X30_Y17_N10
\inst|ram_buf_size[2]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[2]~11_combout\ = (\inst3|outb\(2) & ((GND) # (!\inst|ram_buf_size[1]~10\))) # (!\inst3|outb\(2) & (\inst|ram_buf_size[1]~10\ $ (GND)))
-- \inst|ram_buf_size[2]~12\ = CARRY((\inst3|outb\(2)) # (!\inst|ram_buf_size[1]~10\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101010101111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(2),
	datad => VCC,
	cin => \inst|ram_buf_size[1]~10\,
	combout => \inst|ram_buf_size[2]~11_combout\,
	cout => \inst|ram_buf_size[2]~12\);

-- Location: LCCOMB_X30_Y17_N12
\inst|ram_buf_size[3]~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[3]~13_combout\ = (\inst3|outb\(3) & (\inst|ram_buf_size[2]~12\ & VCC)) # (!\inst3|outb\(3) & (!\inst|ram_buf_size[2]~12\))
-- \inst|ram_buf_size[3]~14\ = CARRY((!\inst3|outb\(3) & !\inst|ram_buf_size[2]~12\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100000011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst3|outb\(3),
	datad => VCC,
	cin => \inst|ram_buf_size[2]~12\,
	combout => \inst|ram_buf_size[3]~13_combout\,
	cout => \inst|ram_buf_size[3]~14\);

-- Location: LCCOMB_X30_Y17_N14
\inst|ram_buf_size[4]~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[4]~15_combout\ = (\inst3|outb\(4) & ((GND) # (!\inst|ram_buf_size[3]~14\))) # (!\inst3|outb\(4) & (\inst|ram_buf_size[3]~14\ $ (GND)))
-- \inst|ram_buf_size[4]~16\ = CARRY((\inst3|outb\(4)) # (!\inst|ram_buf_size[3]~14\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101010101111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(4),
	datad => VCC,
	cin => \inst|ram_buf_size[3]~14\,
	combout => \inst|ram_buf_size[4]~15_combout\,
	cout => \inst|ram_buf_size[4]~16\);

-- Location: LCCOMB_X30_Y17_N16
\inst|ram_buf_size[5]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[5]~17_combout\ = (\inst3|outb\(5) & (\inst|ram_buf_size[4]~16\ & VCC)) # (!\inst3|outb\(5) & (!\inst|ram_buf_size[4]~16\))
-- \inst|ram_buf_size[5]~18\ = CARRY((!\inst3|outb\(5) & !\inst|ram_buf_size[4]~16\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100000011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst3|outb\(5),
	datad => VCC,
	cin => \inst|ram_buf_size[4]~16\,
	combout => \inst|ram_buf_size[5]~17_combout\,
	cout => \inst|ram_buf_size[5]~18\);

-- Location: LCCOMB_X30_Y17_N20
\inst|ram_buf_size[7]~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[7]~21_combout\ = \inst|ram_buf_size[6]~20\ $ (!\inst3|outb\(7))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \inst3|outb\(7),
	cin => \inst|ram_buf_size[6]~20\,
	combout => \inst|ram_buf_size[7]~21_combout\);

-- Location: LCCOMB_X25_Y19_N14
\inst|Equal2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal2~0_combout\ = (!\inst3|outa\(2) & (!\inst3|outa\(0) & (\inst3|outa\(1) & \inst|Equal0~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outa\(2),
	datab => \inst3|outa\(0),
	datac => \inst3|outa\(1),
	datad => \inst|Equal0~3_combout\,
	combout => \inst|Equal2~0_combout\);

-- Location: LCCOMB_X25_Y19_N22
\inst|Selector2~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector2~4_combout\ = (\inst|Equal2~0_combout\) # ((\inst|ddsSta.DDS_PAUSE~q\ & \inst|Selector2~5_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|Equal2~0_combout\,
	datac => \inst|ddsSta.DDS_PAUSE~q\,
	datad => \inst|Selector2~5_combout\,
	combout => \inst|Selector2~4_combout\);

-- Location: FF_X25_Y19_N23
\inst|ddsSta.DDS_PAUSE\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector2~4_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ddsSta.DDS_PAUSE~q\);

-- Location: LCCOMB_X30_Y17_N2
\inst|ram_buf_size[7]~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|ram_buf_size[7]~23_combout\ = (\fsmc_resetn~input_o\ & (!\fsmc_ab[0]~input_o\ & \inst|ddsSta.DDS_PAUSE~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fsmc_resetn~input_o\,
	datac => \fsmc_ab[0]~input_o\,
	datad => \inst|ddsSta.DDS_PAUSE~q\,
	combout => \inst|ram_buf_size[7]~23_combout\);

-- Location: FF_X30_Y17_N21
\inst|ram_buf_size[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[7]~21_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(7));

-- Location: LCCOMB_X29_Y17_N28
\inst|RAM_ADDR~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~12_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (\inst|addr_set\(6))) # (!\inst|RAM_ADDR[0]~3_combout\ & (((!\inst|LessThan1~14_combout\ & \inst|Add1~12_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|addr_set\(6),
	datab => \inst|RAM_ADDR[0]~3_combout\,
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|Add1~12_combout\,
	combout => \inst|RAM_ADDR~12_combout\);

-- Location: FF_X29_Y17_N29
\inst|RAM_ADDR[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~12_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(6));

-- Location: FF_X30_Y17_N17
\inst|ram_buf_size[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[5]~17_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(5));

-- Location: FF_X30_Y17_N15
\inst|ram_buf_size[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[4]~15_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(4));

-- Location: FF_X30_Y17_N13
\inst|ram_buf_size[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[3]~13_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(3));

-- Location: FF_X30_Y17_N11
\inst|ram_buf_size[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[2]~11_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(2));

-- Location: FF_X30_Y17_N9
\inst|ram_buf_size[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|ram_buf_size[1]~9_combout\,
	ena => \inst|ram_buf_size[7]~23_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|ram_buf_size\(1));

-- Location: LCCOMB_X29_Y17_N12
\inst|LessThan1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~1_cout\ = CARRY((!\inst|ram_buf_size\(0) & \inst|RAM_ADDR\(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_buf_size\(0),
	datab => \inst|RAM_ADDR\(0),
	datad => VCC,
	cout => \inst|LessThan1~1_cout\);

-- Location: LCCOMB_X29_Y17_N14
\inst|LessThan1~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~3_cout\ = CARRY((\inst|RAM_ADDR\(1) & (\inst|ram_buf_size\(1) & !\inst|LessThan1~1_cout\)) # (!\inst|RAM_ADDR\(1) & ((\inst|ram_buf_size\(1)) # (!\inst|LessThan1~1_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(1),
	datab => \inst|ram_buf_size\(1),
	datad => VCC,
	cin => \inst|LessThan1~1_cout\,
	cout => \inst|LessThan1~3_cout\);

-- Location: LCCOMB_X29_Y17_N16
\inst|LessThan1~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~5_cout\ = CARRY((\inst|RAM_ADDR\(2) & ((!\inst|LessThan1~3_cout\) # (!\inst|ram_buf_size\(2)))) # (!\inst|RAM_ADDR\(2) & (!\inst|ram_buf_size\(2) & !\inst|LessThan1~3_cout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(2),
	datab => \inst|ram_buf_size\(2),
	datad => VCC,
	cin => \inst|LessThan1~3_cout\,
	cout => \inst|LessThan1~5_cout\);

-- Location: LCCOMB_X29_Y17_N18
\inst|LessThan1~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~7_cout\ = CARRY((\inst|RAM_ADDR\(3) & (\inst|ram_buf_size\(3) & !\inst|LessThan1~5_cout\)) # (!\inst|RAM_ADDR\(3) & ((\inst|ram_buf_size\(3)) # (!\inst|LessThan1~5_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(3),
	datab => \inst|ram_buf_size\(3),
	datad => VCC,
	cin => \inst|LessThan1~5_cout\,
	cout => \inst|LessThan1~7_cout\);

-- Location: LCCOMB_X29_Y17_N20
\inst|LessThan1~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~9_cout\ = CARRY((\inst|RAM_ADDR\(4) & ((!\inst|LessThan1~7_cout\) # (!\inst|ram_buf_size\(4)))) # (!\inst|RAM_ADDR\(4) & (!\inst|ram_buf_size\(4) & !\inst|LessThan1~7_cout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(4),
	datab => \inst|ram_buf_size\(4),
	datad => VCC,
	cin => \inst|LessThan1~7_cout\,
	cout => \inst|LessThan1~9_cout\);

-- Location: LCCOMB_X29_Y17_N22
\inst|LessThan1~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~11_cout\ = CARRY((\inst|RAM_ADDR\(5) & (\inst|ram_buf_size\(5) & !\inst|LessThan1~9_cout\)) # (!\inst|RAM_ADDR\(5) & ((\inst|ram_buf_size\(5)) # (!\inst|LessThan1~9_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|RAM_ADDR\(5),
	datab => \inst|ram_buf_size\(5),
	datad => VCC,
	cin => \inst|LessThan1~9_cout\,
	cout => \inst|LessThan1~11_cout\);

-- Location: LCCOMB_X29_Y17_N24
\inst|LessThan1~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~13_cout\ = CARRY((\inst|ram_buf_size\(6) & (\inst|RAM_ADDR\(6) & !\inst|LessThan1~11_cout\)) # (!\inst|ram_buf_size\(6) & ((\inst|RAM_ADDR\(6)) # (!\inst|LessThan1~11_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ram_buf_size\(6),
	datab => \inst|RAM_ADDR\(6),
	datad => VCC,
	cin => \inst|LessThan1~11_cout\,
	cout => \inst|LessThan1~13_cout\);

-- Location: LCCOMB_X29_Y17_N26
\inst|LessThan1~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~14_combout\ = (\inst|RAM_ADDR\(7) & ((\inst|LessThan1~13_cout\) # (!\inst|ram_buf_size\(7)))) # (!\inst|RAM_ADDR\(7) & (\inst|LessThan1~13_cout\ & !\inst|ram_buf_size\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011111100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \inst|RAM_ADDR\(7),
	datad => \inst|ram_buf_size\(7),
	cin => \inst|LessThan1~13_cout\,
	combout => \inst|LessThan1~14_combout\);

-- Location: LCCOMB_X29_Y17_N4
\inst|RAM_ADDR~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~4_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (((\inst|addr_set\(0))))) # (!\inst|RAM_ADDR[0]~3_combout\ & (\inst|Add1~0_combout\ & ((!\inst|LessThan1~14_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add1~0_combout\,
	datab => \inst|addr_set\(0),
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|RAM_ADDR[0]~3_combout\,
	combout => \inst|RAM_ADDR~4_combout\);

-- Location: FF_X29_Y17_N5
\inst|RAM_ADDR[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~4_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(0));

-- Location: LCCOMB_X30_Y19_N10
\inst|addr_set[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|addr_set[1]~feeder_combout\ = \inst3|outb\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst3|outb\(1),
	combout => \inst|addr_set[1]~feeder_combout\);

-- Location: FF_X30_Y19_N11
\inst|addr_set[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|addr_set[1]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|addr_set[0]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|addr_set\(1));

-- Location: LCCOMB_X29_Y17_N6
\inst|RAM_ADDR~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~7_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (((\inst|addr_set\(1))))) # (!\inst|RAM_ADDR[0]~3_combout\ & (\inst|Add1~2_combout\ & ((!\inst|LessThan1~14_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|Add1~2_combout\,
	datab => \inst|addr_set\(1),
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|RAM_ADDR[0]~3_combout\,
	combout => \inst|RAM_ADDR~7_combout\);

-- Location: FF_X29_Y17_N7
\inst|RAM_ADDR[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~7_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(1));

-- Location: LCCOMB_X29_Y17_N2
\inst|RAM_ADDR~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~9_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (\inst|addr_set\(3))) # (!\inst|RAM_ADDR[0]~3_combout\ & (((\inst|Add1~6_combout\ & !\inst|LessThan1~14_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|addr_set\(3),
	datab => \inst|Add1~6_combout\,
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|RAM_ADDR[0]~3_combout\,
	combout => \inst|RAM_ADDR~9_combout\);

-- Location: FF_X29_Y17_N3
\inst|RAM_ADDR[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~9_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(3));

-- Location: LCCOMB_X29_Y17_N30
\inst|RAM_ADDR~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_ADDR~11_combout\ = (\inst|RAM_ADDR[0]~3_combout\ & (\inst|addr_set\(5))) # (!\inst|RAM_ADDR[0]~3_combout\ & (((!\inst|LessThan1~14_combout\ & \inst|Add1~10_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000101110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|addr_set\(5),
	datab => \inst|RAM_ADDR[0]~3_combout\,
	datac => \inst|LessThan1~14_combout\,
	datad => \inst|Add1~10_combout\,
	combout => \inst|RAM_ADDR~11_combout\);

-- Location: FF_X29_Y17_N31
\inst|RAM_ADDR[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_ADDR~11_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_ADDR[0]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_ADDR\(5));

-- Location: LCCOMB_X24_Y19_N28
\inst|WideOr11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|WideOr11~0_combout\ = (\inst|ddsSta.SET_FRE_PARA~q\) # ((\inst|ddsSta.DDS_PAUSE~q\) # ((\inst|ddsSta.SET_FRE_RANGE~q\) # (\inst|ddsSta.SET_ADDR~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.SET_FRE_PARA~q\,
	datab => \inst|ddsSta.DDS_PAUSE~q\,
	datac => \inst|ddsSta.SET_FRE_RANGE~q\,
	datad => \inst|ddsSta.SET_ADDR~q\,
	combout => \inst|WideOr11~0_combout\);

-- Location: LCCOMB_X25_Y17_N10
\inst|Selector23~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector23~0_combout\ = (\inst3|outb\(1) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(1) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(1) & (((\inst|dds_ram_data\(1) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(1),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(1),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector23~0_combout\);

-- Location: FF_X25_Y17_N11
\inst|dds_ram_data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector23~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(1));

-- Location: LCCOMB_X26_Y17_N4
\inst|RAM_DAT[1]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[1]~feeder_combout\ = \inst|dds_ram_data\(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(1),
	combout => \inst|RAM_DAT[1]~feeder_combout\);

-- Location: FF_X26_Y17_N5
\inst|RAM_DAT[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[1]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(1));

-- Location: LCCOMB_X29_Y19_N10
\inst|Selector22~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector22~0_combout\ = (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(2)) # ((\inst|dds_ram_data\(2) & \inst|WideOr11~0_combout\)))) # (!\inst|ddsSta.WR_ONE_BYTE~q\ & (((\inst|dds_ram_data\(2) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.WR_ONE_BYTE~q\,
	datab => \inst3|outb\(2),
	datac => \inst|dds_ram_data\(2),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector22~0_combout\);

-- Location: FF_X29_Y19_N11
\inst|dds_ram_data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector22~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(2));

-- Location: LCCOMB_X26_Y17_N14
\inst|RAM_DAT[2]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[2]~feeder_combout\ = \inst|dds_ram_data\(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(2),
	combout => \inst|RAM_DAT[2]~feeder_combout\);

-- Location: FF_X26_Y17_N15
\inst|RAM_DAT[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[2]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(2));

-- Location: LCCOMB_X25_Y17_N16
\inst|Selector21~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector21~0_combout\ = (\inst3|outb\(3) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(3) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(3) & (((\inst|dds_ram_data\(3) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(3),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(3),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector21~0_combout\);

-- Location: FF_X25_Y17_N17
\inst|dds_ram_data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector21~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(3));

-- Location: LCCOMB_X26_Y17_N0
\inst|RAM_DAT[3]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[3]~feeder_combout\ = \inst|dds_ram_data\(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|dds_ram_data\(3),
	combout => \inst|RAM_DAT[3]~feeder_combout\);

-- Location: FF_X26_Y17_N1
\inst|RAM_DAT[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[3]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(3));

-- Location: LCCOMB_X25_Y17_N26
\inst|Selector20~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector20~0_combout\ = (\inst3|outb\(4) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(4) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(4) & (((\inst|dds_ram_data\(4) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(4),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(4),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector20~0_combout\);

-- Location: FF_X25_Y17_N27
\inst|dds_ram_data[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector20~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(4));

-- Location: LCCOMB_X26_Y17_N2
\inst|RAM_DAT[4]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[4]~feeder_combout\ = \inst|dds_ram_data\(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|dds_ram_data\(4),
	combout => \inst|RAM_DAT[4]~feeder_combout\);

-- Location: FF_X26_Y17_N3
\inst|RAM_DAT[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[4]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(4));

-- Location: LCCOMB_X25_Y17_N4
\inst|Selector19~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector19~0_combout\ = (\inst3|outb\(5) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(5) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(5) & (((\inst|dds_ram_data\(5) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(5),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(5),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector19~0_combout\);

-- Location: FF_X25_Y17_N5
\inst|dds_ram_data[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector19~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(5));

-- Location: LCCOMB_X26_Y17_N8
\inst|RAM_DAT[5]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[5]~feeder_combout\ = \inst|dds_ram_data\(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|dds_ram_data\(5),
	combout => \inst|RAM_DAT[5]~feeder_combout\);

-- Location: FF_X26_Y17_N9
\inst|RAM_DAT[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[5]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(5));

-- Location: LCCOMB_X25_Y17_N14
\inst|Selector18~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector18~0_combout\ = (\inst3|outb\(6) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(6) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(6) & (((\inst|dds_ram_data\(6) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(6),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(6),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector18~0_combout\);

-- Location: FF_X25_Y17_N15
\inst|dds_ram_data[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector18~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(6));

-- Location: LCCOMB_X26_Y17_N26
\inst|RAM_DAT[6]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[6]~feeder_combout\ = \inst|dds_ram_data\(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(6),
	combout => \inst|RAM_DAT[6]~feeder_combout\);

-- Location: FF_X26_Y17_N27
\inst|RAM_DAT[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[6]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(6));

-- Location: LCCOMB_X29_Y19_N0
\inst|Selector17~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector17~0_combout\ = (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(7)) # ((\inst|dds_ram_data\(7) & \inst|WideOr11~0_combout\)))) # (!\inst|ddsSta.WR_ONE_BYTE~q\ & (((\inst|dds_ram_data\(7) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.WR_ONE_BYTE~q\,
	datab => \inst3|outb\(7),
	datac => \inst|dds_ram_data\(7),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector17~0_combout\);

-- Location: FF_X29_Y19_N1
\inst|dds_ram_data[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector17~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(7));

-- Location: LCCOMB_X26_Y17_N12
\inst|RAM_DAT[7]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[7]~feeder_combout\ = \inst|dds_ram_data\(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|dds_ram_data\(7),
	combout => \inst|RAM_DAT[7]~feeder_combout\);

-- Location: FF_X26_Y17_N13
\inst|RAM_DAT[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[7]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(7));

-- Location: LCCOMB_X29_Y19_N18
\inst|Selector16~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector16~0_combout\ = (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(8)) # ((\inst|dds_ram_data\(8) & \inst|WideOr11~0_combout\)))) # (!\inst|ddsSta.WR_ONE_BYTE~q\ & (((\inst|dds_ram_data\(8) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.WR_ONE_BYTE~q\,
	datab => \inst3|outb\(8),
	datac => \inst|dds_ram_data\(8),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector16~0_combout\);

-- Location: FF_X29_Y19_N19
\inst|dds_ram_data[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector16~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(8));

-- Location: LCCOMB_X28_Y17_N4
\inst|RAM_DAT[8]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[8]~feeder_combout\ = \inst|dds_ram_data\(8)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|dds_ram_data\(8),
	combout => \inst|RAM_DAT[8]~feeder_combout\);

-- Location: FF_X28_Y17_N5
\inst|RAM_DAT[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[8]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(8));

-- Location: LCCOMB_X29_Y19_N24
\inst|Selector15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector15~0_combout\ = (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(9)) # ((\inst|dds_ram_data\(9) & \inst|WideOr11~0_combout\)))) # (!\inst|ddsSta.WR_ONE_BYTE~q\ & (((\inst|dds_ram_data\(9) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.WR_ONE_BYTE~q\,
	datab => \inst3|outb\(9),
	datac => \inst|dds_ram_data\(9),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector15~0_combout\);

-- Location: FF_X29_Y19_N25
\inst|dds_ram_data[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector15~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(9));

-- Location: LCCOMB_X26_Y17_N30
\inst|RAM_DAT[9]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[9]~feeder_combout\ = \inst|dds_ram_data\(9)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(9),
	combout => \inst|RAM_DAT[9]~feeder_combout\);

-- Location: FF_X26_Y17_N31
\inst|RAM_DAT[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[9]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(9));

-- Location: LCCOMB_X25_Y17_N8
\inst|Selector14~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector14~0_combout\ = (\inst3|outb\(10) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(10) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(10) & (((\inst|dds_ram_data\(10) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(10),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(10),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector14~0_combout\);

-- Location: FF_X25_Y17_N9
\inst|dds_ram_data[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector14~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(10));

-- Location: LCCOMB_X26_Y17_N24
\inst|RAM_DAT[10]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[10]~feeder_combout\ = \inst|dds_ram_data\(10)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(10),
	combout => \inst|RAM_DAT[10]~feeder_combout\);

-- Location: FF_X26_Y17_N25
\inst|RAM_DAT[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[10]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(10));

-- Location: LCCOMB_X25_Y17_N6
\inst|Selector13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector13~0_combout\ = (\inst3|outb\(11) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(11) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(11) & (((\inst|dds_ram_data\(11) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(11),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(11),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector13~0_combout\);

-- Location: FF_X25_Y17_N7
\inst|dds_ram_data[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector13~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(11));

-- Location: FF_X26_Y17_N23
\inst|RAM_DAT[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	asdata => \inst|dds_ram_data\(11),
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	sload => VCC,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(11));

-- Location: LCCOMB_X30_Y19_N22
\inst3|outb[12]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst3|outb[12]~feeder_combout\ = \fsmc_db[12]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \fsmc_db[12]~input_o\,
	combout => \inst3|outb[12]~feeder_combout\);

-- Location: FF_X30_Y19_N23
\inst3|outb[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst3|wr~clkctrl_outclk\,
	d => \inst3|outb[12]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst3|Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst3|outb\(12));

-- Location: LCCOMB_X29_Y19_N6
\inst|Selector12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector12~0_combout\ = (\inst|ddsSta.WR_ONE_BYTE~q\ & ((\inst3|outb\(12)) # ((\inst|dds_ram_data\(12) & \inst|WideOr11~0_combout\)))) # (!\inst|ddsSta.WR_ONE_BYTE~q\ & (((\inst|dds_ram_data\(12) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|ddsSta.WR_ONE_BYTE~q\,
	datab => \inst3|outb\(12),
	datac => \inst|dds_ram_data\(12),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector12~0_combout\);

-- Location: FF_X29_Y19_N7
\inst|dds_ram_data[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector12~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(12));

-- Location: LCCOMB_X26_Y17_N28
\inst|RAM_DAT[12]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[12]~feeder_combout\ = \inst|dds_ram_data\(12)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(12),
	combout => \inst|RAM_DAT[12]~feeder_combout\);

-- Location: FF_X26_Y17_N29
\inst|RAM_DAT[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[12]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(12));

-- Location: LCCOMB_X25_Y17_N20
\inst|Selector11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector11~0_combout\ = (\inst3|outb\(13) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(13) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(13) & (((\inst|dds_ram_data\(13) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(13),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(13),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector11~0_combout\);

-- Location: FF_X25_Y17_N21
\inst|dds_ram_data[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector11~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(13));

-- Location: LCCOMB_X26_Y17_N6
\inst|RAM_DAT[13]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[13]~feeder_combout\ = \inst|dds_ram_data\(13)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(13),
	combout => \inst|RAM_DAT[13]~feeder_combout\);

-- Location: FF_X26_Y17_N7
\inst|RAM_DAT[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[13]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(13));

-- Location: LCCOMB_X25_Y17_N30
\inst|Selector10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector10~0_combout\ = (\inst3|outb\(14) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(14) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(14) & (((\inst|dds_ram_data\(14) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(14),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(14),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector10~0_combout\);

-- Location: FF_X25_Y17_N31
\inst|dds_ram_data[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector10~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(14));

-- Location: LCCOMB_X26_Y17_N16
\inst|RAM_DAT[14]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[14]~feeder_combout\ = \inst|dds_ram_data\(14)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(14),
	combout => \inst|RAM_DAT[14]~feeder_combout\);

-- Location: FF_X26_Y17_N17
\inst|RAM_DAT[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[14]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(14));

-- Location: LCCOMB_X25_Y17_N24
\inst|Selector9~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Selector9~0_combout\ = (\inst3|outb\(15) & ((\inst|ddsSta.WR_ONE_BYTE~q\) # ((\inst|dds_ram_data\(15) & \inst|WideOr11~0_combout\)))) # (!\inst3|outb\(15) & (((\inst|dds_ram_data\(15) & \inst|WideOr11~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst3|outb\(15),
	datab => \inst|ddsSta.WR_ONE_BYTE~q\,
	datac => \inst|dds_ram_data\(15),
	datad => \inst|WideOr11~0_combout\,
	combout => \inst|Selector9~0_combout\);

-- Location: FF_X25_Y17_N25
\inst|dds_ram_data[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|wr~clkctrl_outclk\,
	d => \inst|Selector9~0_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \ALT_INV_fsmc_ab[0]~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|dds_ram_data\(15));

-- Location: LCCOMB_X26_Y17_N18
\inst|RAM_DAT[15]~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|RAM_DAT[15]~feeder_combout\ = \inst|dds_ram_data\(15)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|dds_ram_data\(15),
	combout => \inst|RAM_DAT[15]~feeder_combout\);

-- Location: FF_X26_Y17_N19
\inst|RAM_DAT[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \CLK~inputclkctrl_outclk\,
	d => \inst|RAM_DAT[15]~feeder_combout\,
	clrn => \fsmc_resetn~inputclkctrl_outclk\,
	ena => \inst|RAM_DAT[15]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|RAM_DAT\(15));

-- Location: M9K_X27_Y17_N0
\inst1|altsyncram_component|auto_generated|ram_block1a0\ : cycloneive_ram_block
-- pragma translate_off
GENERIC MAP (
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	logical_ram_name => "DDS_RAM:inst1|altsyncram:altsyncram_component|altsyncram_1gf1:auto_generated|ALTSYNCRAM",
	operation_mode => "single_port",
	port_a_address_clear => "none",
	port_a_address_width => 8,
	port_a_byte_enable_clock => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "clock0",
	port_a_data_width => 18,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 255,
	port_a_logical_ram_depth => 256,
	port_a_logical_ram_width => 16,
	port_a_read_during_write_mode => "new_data_with_nbe_read",
	port_b_address_width => 8,
	port_b_data_width => 18,
	ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
	portawe => \inst|RAM_WEN~q\,
	portare => VCC,
	clk0 => \inst|RAM_CLK~clkctrl_outclk\,
	portadatain => \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\);
END structure;


